index

title: “CHIP1 DV Plan”

Goals

• DV
  • Verify all CHIP1 IP features by running dynamic simulations with a SV/UVM based testbench
  • Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
• FPV
  • Verify TileLink device protocol compliance with an SVA based testbench

Current status

• [Design & verification stage]({{< relref “hw” >}})
  • [HW development stages]({{< relref “doc/project/development_stages” >}})
• Simulation results

Design features

For detailed information on CHIP1 design features, please see the [CHIP1 HWIP technical specification]({{< relref “hw/ip/chip1/doc” >}}).

Testbench architecture

CHIP1 testbench has been constructed based on the [CIP testbench architecture]({{< relref “hw/dv/sv/cip_lib/doc” >}}).

Block diagram

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Top level testbench

Top level testbench is located at hw/ip/chip1/dv/tb/tb.sv. It instantiates the CHIP1 DUT module hw/ip/chip1/rtl/chip1.sv.
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db:

• [Clock and reset interface]({{< relref “hw/dv/sv/common_ifs” >}})
• [TileLink host interface]({{< relref “hw/dv/sv/tl_agent/README.md” >}})
• CHIP1 IOs
• Interrupts ([pins_if]({{< relref “hw/dv/sv/common_ifs” >}})
• Alerts ([pins_if]({{< relref “hw/dv/sv/common_ifs” >}})
• Devmode ([pins_if]({{< relref “hw/dv/sv/common_ifs” >}})

Common DV utility components

The following utilities provide generic helper tasks and functions to perform activities that are common across the project:

• [dv_utils_pkg]({{< relref “hw/dv/sv/dv_utils/README.md” >}})
• [csr_utils_pkg]({{< relref “hw/dv/sv/csr_utils/README.md” >}})

Compile-time configurations

[list compile time configurations, if any and what are they used for]

Global types & methods

All common types and methods defined at the package level can be found in
chip1_env_pkg. Some of them in use are:

[list a few parameters, types & methods; no need to mention all]

SPI Agent

[Describe here or add link to its README]

APB Agent

[Describe here or add link to its README]

UVC/agent 1

[Describe here or add link to its README]

UVC/agent 2

[Describe here or add link to its README]

Reference models

[Describe reference models in use if applicable, example: SHA256/HMAC]

Stimulus strategy

Test sequences

All test sequences reside in hw/ip/chip1/dv/env/seq_lib.
The chip1_base_vseq virtual sequence is extended from cip_base_vseq and serves as a starting point.
All test sequences are extended from chip1_base_vseq.
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:

• task 1:
• task 2:

Functional coverage

To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model.
The following covergroups have been developed to prove that the test intent has been adequately met:

• cg1:
• cg2:

Self-checking strategy

Scoreboard

The chip1_scoreboard is primarily used for end to end checking.
It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:

• analysis port1:
• analysis port2:

Assertions

• TLUL assertions: The tb/chip1_bind.sv binds the tlul_assert [assertions]({{< relref “hw/ip/tlul/doc/TlulProtocolChecker.md” >}}) to the IP to ensure TileLink interface protocol compliance.
• Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
• assert prop 1:
• assert prop 2:

Building and running tests

We are using our in-house developed [regression tool]({{< relref “hw/dv/tools/README.md” >}}) for building and running our tests and regressions.
Please take a look at the link for detailed information on the usage, capabilities, features and known issues.
Here’s how to run a smoke test:

$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/chip1/dv/chip1_sim_cfg.hjson -i chip1_smoke

Testplan

{{</* testplan “hw/ip/chip1/data/chip1_testplan.hjson” */>}}